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Extra info for Advances in Electronic Testing: Challenges and Methodologies
Advances in Electronic Testing: Challenges and Methodologies 29 In general, a threefold approach is best: First, logic tests are a key part of any test methodology. Second, the vectors may be generated with the stuck-at model, but they do 14 not have to be graded that way . Third, test application conditions are as important as the vectors themselves. g. bridging faults), then it is 15 important to use stuck-at based logic tests effectively. If an “n-detect” ATPG is available, it should be used.
Thus a scan test with 92% single stuck-at fault coverage had lower overall defect coverage than a combined scan and functional test with only 82% single stuck-at fault coverage (see Figure 1-26). Figure 1-26: Effectiveness of tests versus fault . 2 Effectiveness of IDDQ, Scan, At-speed Tests This experiment was reported at ITC in 1996 . Five test types were applied to a 25K gates synthesized standard cell design (a small to medium sized ASIC at the Advances in Electronic Testing: Challenges and Methodologies 35 time): slow speed scan, AC scan (same vectors, clocked faster), IDDQ, slow functional and at-speed functional.
At the most obvious level, decisions made by routing tools determine which wires are likely to short and which aren’t. Even adjacent wire spacing can be controlled. This section explores two more subtle mechanisms, both relating to low power design and thus appearing in advanced manufacturing technologies. Additional discussion of design related defects is available in , . Multi-VT Libraries Transistor off current and drive current both depend on threshold voltage, as shown in Figure 1-10.